The following documents are incorporated by reference herein:    1. The heterogeneous integration of optical interconnections into integrated microsystems. Jokerst, N. M., et al., 2003 IEEE Journal of Selected Topics in Quantum Electronics, Vol. 9, pp. 350-360.    2. Heterogeneous Integration of Compound Semiconductors. Moutanabbir, Oussama and Gosele, Ulrich. 2010, The Annual Review of Materials Research, Vol. 40, pp. 469-500.    3. New Solder Bumping Technology and Adapted Assembly Processes for 100 μm Pitch Flip-Chip-Technology Using Capillary Flow or No Flow Underfill. Florian Schüβler, Rainer Dohle, Thomas Oppert, Ghassem Azdasht, Georgi Georqiev, Jörg Franke. 2009. The SMTA International Conference Proceedings.    4. Exfoliation of GaAs Caused by MeV 1H and 4He Ion Implantation at (100), (110) Axial and Random Orientations. Rauhala, E. and Räisänen, J. 3, 1994, Nuclear Instruments and Methods in Physics Research Section B: Beam Interactions with Materials and Atoms, Vol. 94, pp. 245-250.    5. Blistering/exfoliation kinetics of GaAs by hydrogen and helium implantations. Woo, et al., 17-18, 2009, Surface & Coatings Technology, Vol. 203, pp. 2370-2374.    6. Wafer-to-Wafer Bonding for Microstructure Formation. Schmidt, Martin A. 8, 1998, PROCEEDINGS OF THE IEEE, Vol. 86, pp. 1575-1585.    7. Technologies for 3D Wafer Level Heterogeneous Integration. M. J. Wolf, P. Ramm, A. Klumpp, H. Reichl. s.l.: EDA Publishing/DTIP 2008, 2008.    8. Self-Assembly Process for Chip-to-Wafer Three-Dimensional Integration. T. Fukushima, Y. Yamada, H. Kikuchi, T. Tanaka, M. Koyanagi. 2007. IEEE Electronic Components and Technology Conference.    9. Pan, Eric TS. Method of integrating epitaxial film onto assembly substrate. U.S. Pat. No. 8,193,078.    10. Pan, Eric TS. Apparatus for making epitaxial film. U.S. Pat. No. 7,905,197.
Systems integration and packaging is evolving along with emerging needs of systems. Mainframe computers drove the development of Multichip Modules (MCMs) by interconnecting multiple chips in a small, horizontal form factor to achieve high signal speed. High-end networking, signal processing, and digital communication demands drive System-on-a-Chip (SoC) by integrating all or most of the system needs on large and complex single chips, representing a confluence of previous product classes through integration of technology and design elements from other system driver classes such as microprocessor, application specific IC (ASICS) and analog/mixed signal circuits. Cell phones and handsets are driving System in Package (SiP) solutions by 3D chip stacking of either bare chips or packaged chips requiring interconnections from chip-to-chip using lateral or vertical integration technologies.
With the continued demand for systems and sub-systems (e.g. electronic, optoelectronic, electromechanical, etc.) having more functionality, higher performance, smaller size, lower cost, and faster time-to-market, advancing heterogeneous technology integration of components from different materials and fabrication processes makes possible many advanced systems (see reference #1 above). To this end, various hybrid integration technologies including heteroepitaxy (see reference #2), flip-chip bonding (see reference #3), layer lift-off and direct bonding see references (2) (4) (5), wafer transfer and bonding—see references (6) (7), micro-robotic pick and place, three-dimensional (3D) stacking and self-assembly (see reference (8)) methods have been explored. But in order to realize heterogeneous integration, new capabilities are needed: process technology, architectures, design methods and tools, and manufacturing test solutions.
Moreover, growth and fabrication procedures optimized for a single device technology often must be compromised to accommodate dissimilar material systems. This forces the costly development of customized processes for every component and prevents the use of low-cost foundries for producing the integrated systems.